Open AccessDesign and Simulation of Silicon Nanowire Tunnel Field Effect Transistor
Author(s) -
Parveen Kumar,
Balwinder Raj
Publication year - 2021
Publication title -
aijr proceedings
Language(s) - English
Resource type - Conference proceedings
ISSN - 2582-3922
DOI - 10.21467/proceedings.114.62
Subject(s) - nanowire , tunnel field effect transistor , subthreshold slope , materials science , field effect transistor , transistor , optoelectronics , silicon , quantum tunnelling , radius , gate oxide , silicon nanowires , electrical engineering , engineering , computer science , computer security , voltage
This paper analyses the different parameters of tunnel field-effect transistor (TFET) based on silicon Nanowire in vertical nature by using a Gaussian doping profile. The device has been designed using an n-channel P+-I-N+ structure for tunneling junction of TFET with gate-all-around (GAA) Nanowire structure. The gate length has been taken as 100 nm using silicon Nanowire to obtain the various parameters such as ON-current (ION), OFF-current (IOFF), current ratio, and Subthreshold slope (SS) by applying different values of work function at the gate, the radius of Nanowire and oxide thickness of the device. The simulations are performed on Silvaco TCAD which gives a better parametric analysis over conventional tunnel field-effect transistor.