z-logo
open-access-imgOpen Access
Energy Efficient UART Design Using Virtex-4, Virtex-5 and Virtex-6 FPGA
Author(s) -
Keshav Kumar,
Amanpreet Kaur
Publication year - 2019
Publication title -
gyancity journal of electronics and computer science
Language(s) - English
Resource type - Journals
ISSN - 2446-2918
DOI - 10.21058/gjecs.2019.41002
Subject(s) - virtex , universal asynchronous receiver/transmitter , computer science , field programmable gate array , embedded system , telecommunications , chip

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here
Accelerating Research

Address

John Eccles House
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom