Open AccessA Real-Time Tsunami Inundation Forecast System Using Vector Supercomputer SX-ACE
Author(s) -
Akihiro Musa,
Takashi Abe,
Takuya Inoue,
Hiroaki Hokari,
Yoichi Murashima,
Yoshiyuki Kido,
Susumu Date,
Shinsuke Shimojo,
Shunichi Koshimura,
Hiroaki Kobayashi
Publication year - 2018
Publication title -
journal of disaster research
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.332
H-Index - 18
eISSN - 1883-8030
pISSN - 1881-2473
DOI - 10.20965/jdr.2018.p0234
Subject(s) - supercomputer , xeon , computer science , xeon phi , computation , grid , parallel computing , geology , algorithm , geodesy
Tsunami disasters can cause serious casualties and damage to social infrastructures. An early understanding of disaster states is required in order to advise evacuations and plan rescues and recoveries. We have developed a real-time tsunami inundation forecast system using a vector supercomputer SX-ACE. The system can complete a tsunami inundation and damage estimation for coastal city regions at the resolution of a 10 m grid size in under 20 minutes, and distribute tsunami inundation and infrastructure damage information to local governments in Japan. We also develop a new configuration for the computational domain, which is changed from rectangles to polygons and called a polygonal domain, in order to effectively simulate in the entire coast of Japan. Meanwhile, new supercomputers have been developed, and their peak performances have increased year by year. In 2016, a new Xeon Phi processor called Knights Landing was released for high-performance computing. In this paper, we present an overview of our real-time tsunami inundation forecast system and the polygonal domain, which can decrease the amount of computation in a simulation, and then discuss its performance on a vector supercomputer SX-ACE and a supercomputer system based on Intel Xeon Phi. We also clarify that the real-time tsunami inundation forecast system requires the efficient vector processing of a supercomputer with high-performance cores.