Open AccessPower Efficient, Low Noise 2-5 GHz Phase Locked Loop
Author(s) -
Vazgen Melikyan,
Armen Durgaryan,
H. P. Petrosyan,
A.G. Stepanyan
Publication year - 2011
Publication title -
èlektronika i svâzʹ
Language(s) - English
Resource type - Journals
eISSN - 2312-1807
pISSN - 1811-4512
DOI - 10.20535/2312-1807.2011.16.4.244797
Subject(s) - phase locked loop , pll multibit , voltage controlled oscillator , phase noise , jitter , noise (video) , loop (graph theory) , power (physics) , control theory (sociology) , electronic engineering , phase detector , voltage , computer science , electrical engineering , physics , engineering , mathematics , combinatorics , artificial intelligence , quantum mechanics , image (mathematics) , control (management)
A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead