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Effect of source/drain overlap region on device performance in a‐IGZO thin‐film transistors
Author(s) -
Nam DongHo,
Choi Kwangil,
Park SungSoo,
Park JeongGyu,
Choi WonHo,
Han InShik,
Lee HiDeok,
Jeong JaeKyeong,
Lee GaWon
Publication year - 2009
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1889/jsid17.9.735
Subject(s) - thin film transistor , materials science , offset (computer science) , optoelectronics , channel length modulation , threshold voltage , transistor , amorphous solid , voltage , electrical engineering , nanotechnology , computer science , crystallography , chemistry , engineering , layer (electronics) , programming language
— In this paper, the effect of source/drain overlap length on the amorphous indium gallium zinc oxide (a‐IGZO) TFT performance has been investigated. Results of this paper show that as source/drain overlap length decreases to a negative value forming S/D offset, the threshold voltage and S parameters of a‐IGZO TFTs increased and the field‐effect mobility decreased. The V T variation increases sharply as the channel length decreases because of the large resistance R offset when it is formed at a‐IGZO source/drain. In the experiment, R offset of each 1 μm, evaluated from the transfer length method (TLM), shows approximately 54–66 kΩ. This means thatthe source/drain overlap length is a very important control parameter for uniform device characteristics of a‐IGZO TFTs.