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Asymmetric source/drain offset structure for reduced leakage current in polycrystalline‐silicon thin‐film transistors
Author(s) -
Lee WonKyu,
Park HyunSang,
Jeong ByoungSeong,
Choi Joonhoo,
Kim ChiWoo,
Hong Yongtaek,
Han MinKoo
Publication year - 2009
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1889/jsid17.6.501
Subject(s) - thin film transistor , polycrystalline silicon , materials science , optoelectronics , transistor , offset (computer science) , silicon , annealing (glass) , doping , fabrication , ion implantation , electrical engineering , nanotechnology , ion , composite material , voltage , computer science , chemistry , programming language , medicine , alternative medicine , engineering , organic chemistry , layer (electronics) , pathology
— An asymmetric source/drain offset structured (AOS) polycrystalline‐silicon (poly‐Si) thin‐film transistor (TFT) has ben developed by employing alternating magnetic‐field‐enhanced rapid thermal annealing (AMFERTA). The realized AOS poly‐Si TFT, with long drain‐side offset length L Off1 and short source‐side offset length L Off2 , considerably suppresses leakage current without sacrificing ON‐current. The offset regions of the AOS TFT are naturally lightly doped due to the diffusion of n + ions by AMFERTA crystallization. The fabrication process of the AOS TFT does not require any additional offset mask step or doping process. Experimental results show that the leakage current is considerably suppressed when the drain‐side offset length L Off1 is larger than 1.25 μm.