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46.2: System Architecture and FPGA‐Implementation of the SSC Local Dimming Processor for an Edge‐Lit Serial TV
Author(s) -
Jung Tobias,
Albrecht Marc,
Schäfer Daniel,
Xu Chihao
Publication year - 2011
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3621410
Subject(s) - field programmable gate array , computer science , clipping (morphology) , preprocessor , computer hardware , power consumption , enhanced data rates for gsm evolution , pixel , embedded system , power (physics) , artificial intelligence , philosophy , linguistics , physics , quantum mechanics
We present an efficient hardware implementation of our local dimming processor which consists of a preprocessor (Condenser), the Sorted Sector Covering (SSC) algorithm and a postprocessor (Pixel Compensation) in a low‐cost FPGA. The system runs in a typical 40″ Full‐HD TV set with edge‐ LED. An equivalent visual quality like the undimmed version has been achieved, while the power consumption for the BLU with four LED units is reduced by 21%. In case of tolerating limited clipping artifacts, the power consumption can even be reduced by 46%.