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27.3: 1.2 Gbps GDDR3 Physical Layer for 3D AMOLED Panel
Author(s) -
Hwang MoonSang,
Shin Kwangsuk,
Choe Won Jun,
Kim Sang Soo,
Chi HanKyu,
Jeong DeogKyoon
Publication year - 2011
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3621322
Subject(s) - skew , phy , chip , amoled , computer science , cmos , electronic engineering , controller (irrigation) , layer (electronics) , physical layer , materials science , engineering , telecommunications , agronomy , composite material , wireless , biology , active matrix , thin film transistor
A 1.2‐Gbps GDDR3 physical layer (PHY) circuit for flat panel displays is presented. To reduce the channel skew and to make the clock robust against power supply noise, an automatic skewcalibration algorithm and a coarse lock detector with hysteresis are proposed. The GDDR3 PHY has been integrated in a timing controller chip fabricated in standard 0.13‐μm CMOS process.