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9.3: Control of Threshold Voltage in Back Channel Etch Type Amorphous Indium Gallium Zinc Oxide Thin Film Transistors
Author(s) -
Lee Seung Min,
Ryoo Chang Il,
Park Jae Wook,
Han Joonsoo,
Kim DaeWon,
Kim YongYub,
Kang ImKuk,
Seo KyungHan,
Koh Young Ju,
Han DongMin,
Choi YongHo,
Seo HyunSik,
Kim Bong Chul,
Cha Soo Youle,
Bae JongUk,
Kim Chang Dong,
Jun Myungchul,
Hwang Yong Kee
Publication year - 2011
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3621002
Subject(s) - thin film transistor , materials science , optoelectronics , passivation , threshold voltage , transistor , amorphous solid , voltage , electrical engineering , electronic engineering , layer (electronics) , nanotechnology , engineering , chemistry , organic chemistry
Tuning the process pressure at the deposition of the passivation layers has been suggested in the way of controlling the threshold voltage of a‐IGZO TFTs, making it possible to employ gate driver integration. It has showed that V th linearly changes with the pressure ΔV th /ΔPressure∼3.5V/100Pa. A 3.2 inch WVGA AMLCD with integrated gate driver circuits were successfully demonstrated using the enhancement mode BCE type bottom gate a‐IGZO TFTs.