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17.4L: LateNews Paper : Contact Resistance and Process Integration Effects on HighPerformance Oxide TFTs with SolutionDeposited Semiconductor and Gate Dielectric Layers
Author(s) -
Heo Jaeseok,
Kim Junghan,
Choi Seungchan,
Park KwonShik,
Kim ChangDong,
Hwang Yong Kee,
Chung InJae,
Meyers Stephen T.,
Anderson Jeremy T.,
Clark Benjamin C.,
Greer Michael,
Jiang Kai,
Grenville Andrew,
Keszler Douglas A.
Publication year - 2010
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3500417
Subject(s) - materials science , reliability (semiconductor) , dielectric , optoelectronics , gate dielectric , contact resistance , oxide , semiconductor , amorphous solid , gate oxide , process (computing) , electronic engineering , engineering physics , transistor , electrical engineering , computer science , nanotechnology , layer (electronics) , metallurgy , engineering , chemistry , voltage , crystallography , operating system , power (physics) , physics , quantum mechanics
Highperformance TFTs with solutiondeposited amorphous oxide semiconductor and gate dielectric layers are fabricated at ≤ 350 °C. The initial performance and stability of these TFTs are investigated with respect to device structure and source/drain materials. Topcontact TFTs exhibit better electrical performance and reliability than bottomcontact devices. Representative topcontact device mobility is 1.90 cm 2 /Vs with an ontooff drain current ratio of 7.0 × 10 8 .