64.3: Design of Partially Cascaded Clock‐Embedded Serial Link Intra‐Panel Interface for a Flat Panel Display System | Zendy

Kim AhReum | Zendy; Choe WonJun | Zendy; Lee SangKeun | Zendy; Kim NamDeog | Zendy; Kim SangSoo | Zendy

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64.3: Design of Partially Cascaded Clock‐Embedded Serial Link Intra‐Panel Interface for a Flat Panel Display System

Author(s) -

Kim AhReum,

Choe WonJun,

Lee SangKeun,

Kim NamDeog,

Kim SangSoo

Publication year - 2009

Publication title -

sid symposium digest of technical papers

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.351

H-Index - 44

eISSN - 2168-0159

pISSN - 0097-966X

DOI - 10.1889/1.3256959

Subject(s) - interface (matter) , computer science , computer hardware , link (geometry) , point to point , embedded system , telecommunications , parallel computing , computer network , bubble , maximum bubble pressure method

A partially cascaded clock‐embedded serial link has been designed as an intra‐panel interface between a timing controller (TCON) and column driver ICs (DICs) in an LCD panel. The proposed link achieves a 60Hz full‐HD display of 10‐bit color depth on only four interface pairs. Compared to a conventional point‐to‐point interface, further reduction of the number of interface lines has been achieved by means of a bandwidth efficient cascaded scheme.

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