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28.3: Pixel Parasitic Capacitance Modification with Embedded Gate Driver on Panel for a‐Si High Resolution Technology Scheme
Author(s) -
Peng JenChieh,
Yan Shuoting,
Hung Owen,
Hsieh TsauHua,
Yang Chiulien,
Pang JiaPang
Publication year - 2009
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3256796
Subject(s) - parasitic capacitance , capacitance , video graphics array , pixel , flat panel display , materials science , compensation (psychology) , optoelectronics , line (geometry) , electrical engineering , electronic engineering , computer science , electrode , engineering , cmos , chemistry , artificial intelligence , psychology , geometry , mathematics , psychoanalysis
The 2.4‐inch VGA (332 ppi) has been fulfilled and demonstrated by a‐Si technology with the modification of pixel parasitic capacitance and embedded a‐Si gate driver on panel. with the pixel design regarding the compensation of parasitic capacitance of source line to pixel ITO electrode, the a‐Si high resolution panel with 332 ppi meets the requirements of electrical and optical performance for TFTLCDs as a result. Also, it shows the opportunity for entry of a‐Si high resolution technology with a lower cost process flow.