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27.4: A 10‐Bit Serial Integration‐Type DAC Architecture for AMLCD Column Drivers
Author(s) -
Kim KiDuk,
Woo YoungJin,
Lee SungWoo,
Jeon YongJoon,
Jeon JinYong,
Yang JunHyeok,
Park KyuSung,
Baek JongHak,
Cho GyuHyeong
Publication year - 2009
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3256792
Subject(s) - integrator , capacitor , cmos , frame (networking) , electronic engineering , computer science , computer hardware , column (typography) , embedded system , engineering , electrical engineering , voltage , bandwidth (computing) , computer network
Abstract A 10‐bit serial integration‐type DAC architecture based on discrete‐time integrator using switched‐capacitor structure is proposed for AMLCD column drivers in this paper. This proposed serial DAC architecture can dramatically reduces its size by minimizing the size of capacitors used for integration using a simple capacitor swapping algorithm per frame. The design of the proposed DAC was dedicated to mobile application and has been fabricated in 0.35μm 3.3V CMOS process.