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27.2: A Buffer Amplifier with Embodied 4‐Bit Interpolation for 10‐Bit AMLCD Column Drivers
Author(s) -
Lee Byunghun,
Kim KiDuk,
Jeon YongJoon,
Lee SungWoo,
Jeon JinYong,
Jung SeungChul,
Yang JunHyeok,
Park KyuSung,
Cho GyuHyeong
Publication year - 2009
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3256790
Subject(s) - buffer amplifier , least significant bit , amplifier , operational amplifier , bit (key) , electronic engineering , buffer (optical fiber) , interpolation (computer graphics) , computer science , 12 bit , differential nonlinearity , current feedback operational amplifier , cmos , electrical engineering , engineering , telecommunications , computer network , frame (networking) , operating system
A buffer amplifier for 10‐bit digital‐to‐analog converter (DAC) with embodied 4‐bit interpolation is proposed for AMLCD column drivers. Under the proposed interpolating scheme, the reference voltage from 6‐bit DAC is interpolated with the voltage generated from 4 bit directly inputted codes in the buffer amplifier. This proposed circuit can reduce the effective size of the DACs, and achieve the accurate channel output maintaining the basic function of the buffer amplifier. The average static current of the proposed buffer amplifier is 1.2μA per each channel and the simulated result of INL and DNL by 0.35μm CMOS process is less than 0.06 and 0.05 LSB.