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P‐39: pLVDS : A New Intra‐Panel Interface for the Future Flat‐Panel Displays with Higher Resolution and Larger Size
Author(s) -
Koh Hwasu
Publication year - 2009
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3256516
Subject(s) - signal integrity , panel data , signal (programming language) , computer science , drop (telecommunication) , flat panel , interface (matter) , transfer (computing) , telecommunications , mathematics , statistics , computer graphics (images) , interconnection , programming language , bubble , maximum bubble pressure method , parallel computing
In this paper, we will present the pLVDS , the newly developed intra‐panel interface standard for the future flat‐panel displays which have higher resolution, more natural image and larger size panel. These panels require much higher data rate with good signal integrity and lower EMI level. To satisfy those requirements, differential point‐to‐point data signal line and differential multi‐drop bus clock signal line architecture with low frequency are chosen. The new signaling protocol was proposed for the efficient data transfer, that is, much lower data rate for the same panel performance. Pre‐emphasis on the Tx driver is adopted for the robust data recovery at the Column Drivers by compensating the frequency dependent channel loss on the large size panel.