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P‐4: Integrated a‐Si TFT Gate Driver with Reducing Clock Duty Ratio
Author(s) -
Chen ShyhFeng,
Chang LeeHsun,
Chen JingRu,
Lin ShihChyn,
Yu ChiuMei,
Hsu JeHao,
Chen IChun
Publication year - 2009
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3256474
Subject(s) - gate driver , thin film transistor , duty cycle , electrical engineering , line (geometry) , materials science , computer science , optoelectronics , engineering , voltage , nanotechnology , mathematics , geometry , layer (electronics)
A 15 inch wide type LCD using an integrated a‐Si TFT gate driver has been developed. The gate driver driven by the clocks with the duty ratio of lower than 50% can use only one large output TFT to charge and discharge the gate line so that the pull‐down TFT in the gate driver can be eliminated and the required layout area for the gate driver can be also reduced.