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45.3: Cost Effective 60Hz FHD LCD with 800Mbps AiPi Technology
Author(s) -
Nam Hyoungsik,
Oh Kwan Young,
Kim Seon Ki,
Kim Nam Deog,
Berkeley Brian H.,
Kim Sang Soo,
Lee Yongjae,
Nakajima Keiichi
Publication year - 2008
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3069756
Subject(s) - interface (matter) , computer science , point to point , controller (irrigation) , computer hardware , scheme (mathematics) , simple (philosophy) , point (geometry) , embedded system , topology (electrical circuits) , engineering , electrical engineering , computer network , parallel computing , mathematics , philosophy , geometry , bubble , epistemology , maximum bubble pressure method , agronomy , biology , mathematical analysis
AiPi technology incorporates an embedded clock and control scheme with a point‐to‐point bus topology, achieving the smallest possible number of interface lines between a timing controller and source drivers. A point‐to‐point architecture enables the data rate to be boosted and the number of interface lines to be reduced because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi‐level signaling resulting in simple clock/data recovery circuitry. A 46″ AiPi‐based 10‐bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini‐LVDS. The measured maximum data rate per one data pair is more than 800Mbps.