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38.3: All‐Digital Phase‐Locked Loop with Low‐Temperature Poly‐Silicon Thin Film Transistor for System‐on‐Glass
Author(s) -
Choi Jinyong,
Min Kyungyoul,
Nam YoungJin,
Yoo Changsik
Publication year - 2008
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3069724
Subject(s) - jitter , thin film transistor , phase locked loop , materials science , transistor , integrator , substrate (aquarium) , optoelectronics , electronic engineering , electrical engineering , engineering , nanotechnology , voltage , oceanography , layer (electronics) , geology
This paper describes an all‐digital phase‐locked loop (ADPLL) for system‐on‐glass (SoG) with low‐temperature poly‐Silicon (LTPS) thin film transistor (TFT). Due to the large variations and mismatches of LTPS TFT, it is very difficult to implement an analog PLL on glass substrate and ADPLL is employed for the timing generation in SoG. The ADPLL is implemented with a 2μm LTPS TFT process technology and consists of 5‐bit delay‐line time‐to‐digital converter (TDC), 7‐bit digitally controlled oscillator (DCO) and digital integrator. with a 20MHz reference clock, the ADPLL is locked within 36 periods of reference clock and shows 930ps peak‐to‐peak jitter.