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P‐143: New Drive Waveforms for High Speed Erase Addressing
Author(s) -
Jung JaeChul,
Kwon Ohyung,
Syn Ho Jung,
Kim Joong Kyun,
Whang KiWoong
Publication year - 2008
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3069510
Subject(s) - waveform , reset (finance) , voltage , jitter , electrode , materials science , electrical engineering , time lag , signal (programming language) , margin (machine learning) , computer science , lag , physics , engineering , computer network , quantum mechanics , machine learning , financial economics , economics , programming language
We propose a new high speed driving waveform which uses a negatively biased voltage to the common electrode and an alternating ramp voltage to the scan electrode during the reset period and an erase address scheme. It showed short discharge time lag under 800nsec, wide address voltage margin over 40V and improved jitter characteristics among different color cells in a 7.5inch test panel with 50inch full HD resolution. Its fast discharge characteristics was attributed to the formation of stronger wall voltage near the middle of the gap during the reset period and the consequent bigger electric field during the scan period which was confirmed by the 3 dimensional emission observation and voltage domain analysis.