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P‐140: A Modified Selective Reset‐Waveform to Minimize Wall‐Voltage Variation During Address‐Period in Full‐HD PDP
Author(s) -
Park Hyung Dal,
Park KiHyung,
Choi ByungTae,
Tae HeungSik,
Hur Ming,
Park SooHo,
Yoo Minsun,
Heo Eun Gi
Publication year - 2008
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3069507
Subject(s) - reset (finance) , waveform , voltage , electrode , materials science , electrical engineering , pulse (music) , control theory (sociology) , computer science , physics , engineering , control (management) , quantum mechanics , artificial intelligence , financial economics , economics
This paper proposes a modified selective reset driving waveform that can lower the potential difference between the scan and address electrodes by applying the address‐bias voltage (V a‐bias ) to the address electrode during the application of the rising pulse of Y‐electrode in the selective reset‐period. This address‐bias voltage (V a‐bias ) plays a role in suppressing the wall‐charge accumulation on the address electrode during the selective reset‐period, thereby contributing to minimizing the wall‐voltage variation during the address‐period and as such allowing the higher voltage difference (=ΔV y ) between the scan low voltage (V sl ) and the negative falling ramp voltage (V nf ) during an address‐period without any misfiring discharge. When adopting the proposed selective reset waveform, the address discharge delay time is observed to be reduced by about 120 ns.