P‐30: A Relation Between an a‐Si: H Integrated Buffer Transistor Resistance and Falling Time of Gate Output Signal

In case of using an a‐Si:H integrated gate driver for TFT‐LCD [1–4], it's important to define gate falling time exactly. Because an a‐Si:H integrated gate driver might degrade with bad environment easily, which result in gate signal delay or decreasing output signal. In other words, a little degradation of a‐Si:H gate driver affects the quality of picture. If a little degradation of a‐Si:H gate driver under special circumstance is inevitable, it's necessary to make a gate driver has so sufficient margin time within one horizontal time that cannot be interfered with next data signal. So, it's necessary to understand what factors affect the a‐Si:H integrated gate output signal. Especially, we focused an a effect of buffer transistor resistance for gate output signal. In our study, with a test a‐Si:H integrated gate driver pattern and simple simulation process, a relation a‐Si:H integrated buffer transistor resistance and gate output signal is analyzed.