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P‐30: A Relation Between an a‐Si: H Integrated Buffer Transistor Resistance and Falling Time of Gate Output Signal
Author(s) -
Kim DoSung,
Jo SungHak,
Jeong SeongHun,
Nam DaeHyun,
Min SoonYoung,
Lee KyungHa,
Shin JongKeun,
Chung In Jae
Publication year - 2008
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3069373
Subject(s) - signal (programming language) , transistor , gate equivalent , gate driver , nand gate , buffer (optical fiber) , degradation (telecommunications) , and gate , sensitivity (control systems) , computer science , logic gate , electrical engineering , optoelectronics , materials science , electronic engineering , gate oxide , engineering , voltage , programming language
In case of using an a‐Si:H integrated gate driver for TFT‐LCD [1–4], it's important to define gate falling time exactly. Because an a‐Si:H integrated gate driver might degrade with bad environment easily, which result in gate signal delay or decreasing output signal. In other words, a little degradation of a‐Si:H gate driver affects the quality of picture. If a little degradation of a‐Si:H gate driver under special circumstance is inevitable, it's necessary to make a gate driver has so sufficient margin time within one horizontal time that cannot be interfered with next data signal. So, it's necessary to understand what factors affect the a‐Si:H integrated gate output signal. Especially, we focused an a effect of buffer transistor resistance for gate output signal. In our study, with a test a‐Si:H integrated gate driver pattern and simple simulation process, a relation a‐Si:H integrated buffer transistor resistance and gate output signal is analyzed.