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P‐26: Thermally Annealed Asymmetric‐Offset Polycrystalline Thin Film Transistor with Low Leakage
Author(s) -
Lee WonKyu,
Han SangMyeon,
Kang DongWon,
Han MinKoo,
Choi Joonhoo,
Kim ChiWoo
Publication year - 2008
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3069369
Subject(s) - materials science , thin film transistor , optoelectronics , annealing (glass) , offset (computer science) , polycrystalline silicon , transistor , doping , power consumption , electrical engineering , voltage , composite material , power (physics) , computer science , physics , layer (electronics) , quantum mechanics , programming language , engineering
We have designed and fabricated a new top gate asymmetric offset structured n‐type depletion mode poly‐Si TFT of which the leakage current was considerably reduced due to successful suppression of electric field near the drain region caused by the asymmetric offset structure. The TFT was fabricated on the glass substrate by employing alternating magnetic field enhanced rapid thermal annealing (AMFERTA). The a‐Si and n+ a‐Si layers were deposited successively, and did not use any other ion doping methods. The asymmetric offset structure could be made without additional processes or masks. This new structure suppressed the leakage current to about 86% of non‐offset structured AMFERTA poly‐Si TFT without considerable sacrifice of on current. This suppression method of leakage current can be helpful to remain the good image quality and save the power consumption of AMOLED panels.