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P‐5: Spacer Technique to Fabricate pSi TFTs with 50nm Nanowire Channels
Author(s) -
Chang ChiaWen,
Chen SzuFen,
Wu ShihChieh,
Lin GuanLiang,
Lei TanFu
Publication year - 2008
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.3069346
Subject(s) - thin film transistor , materials science , polycrystalline silicon , nanowire , photolithography , optoelectronics , controllability , electrode , silicon , transistor , perpendicular , nanotechnology , layer (electronics) , electrical engineering , voltage , engineering , chemistry , mathematics , geometry
In this work, polycrystalline silicon thin‐film transistors (poly‐Si TFTs) with 50‐nm nanowire (NW) channels fabricated without advanced photolithography by using a sidewall spacer formation technique are proposed for the first time. Because the poly gate electrode is perpendicularly across poly‐Si NW channels to form a tri‐gate‐like structure, the proposed poly‐Si NW TFT owns an outstanding gate controllability. In summary, a simple and low‐cost scheme is proposed to fabricate high‐performance poly‐Si NW TFT suitable for future display manufacturing and practical applications.