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Amorphous‐silicon gate‐driver circuits of shared‐node dual pull‐down structure with overlapped output signals
Author(s) -
Cho Hyung Nyuck,
Kim Hae Yeol,
Ryoo Chang,
Choi Seung Chan,
Kim Binn,
Jang Yong Ho,
Yoon Soo Young,
Chun Min Doo,
Park Kwonshik,
Moon Taewoong,
Cho Nam Wook,
Jo Sung Hak,
Kim Sung Ki,
Kim ChangDong,
Kang In Byeong
Publication year - 2008
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1889/1.2835039
Subject(s) - node (physics) , materials science , optoelectronics , thin film transistor , electronic circuit , gate driver , reset (finance) , computer science , electrical engineering , nanotechnology , voltage , engineering , physics , acoustics , layer (electronics) , financial economics , economics
Abstract— A novel gate‐driver circuit using amorphous‐silicon (a‐Si) TFTs has been developed. The circuit has a shared‐node dual pull‐down AC (SDAC) structure with a common‐node controller for two neighboring stages, resulting in a reduced number of TFTs. The overlapped clock signals widen the temperature range for stable operation due to the extended charging time of the inner nodes of the circuit. The accelerated lifetime was found to be over 1000 hours at 60°C with good bias‐temperature‐stress (BTS) characteristics. Accordingly, the a‐Si gate‐driver circuit was successfully integrated into a 14.1‐in. XGA (1024 × RGB × 768) TFT‐LCD panel having a single bank form.