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Modeling of threshold‐voltage‐shift dependency on drain bias in amorphous‐silicon thin‐film transistors in active‐matrix organic light‐emitting‐diode displays
Author(s) -
Miwa Koichi,
Maekawa Yuichi,
Tsujimura Takatoshi
Publication year - 2007
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1889/1.2825103
Subject(s) - amoled , thin film transistor , threshold voltage , active matrix , materials science , optoelectronics , amorphous silicon , channel length modulation , transistor , saturation (graph theory) , diode , oled , overdrive voltage , voltage , amorphous solid , silicon , drain induced barrier lowering , electrical engineering , crystalline silicon , nanotechnology , chemistry , layer (electronics) , mathematics , engineering , organic chemistry , combinatorics
— A theoretical model to interpret appearances of the threshold voltage shift in hydrogenated amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) is developed to better understand the instability of a‐Si:H TFTs for the driving transistors in active‐matrix organic light‐emitting‐diode (AMOLED) displays. This model assumes that the defect creation at channel in a‐Si:H is proportional to the carrier concentration, leading to the defect density varying along the channel depending on the bias conditions. The model interprets a threshold‐voltage‐shift dependency on the drain‐stress bias. The model predicts the threshold voltage shift stressed under a given gate bias applying the drain saturation voltage is 66% of that with zero drain bias, and it even goes down to 50–60% of that when stressed by applying twice the drain saturation voltage.