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55.3: Study on Address Discharge Characteristics Using V t Close‐Curve Analysis in ac PDPs
Author(s) -
Cho ByungGwon,
Tae HeungSik
Publication year - 2007
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2785632
Subject(s) - luminance , electrode , voltage , materials science , reset (finance) , low voltage , biasing , electrical engineering , analytical chemistry (journal) , optoelectronics , physics , optics , chemistry , engineering , chromatography , quantum mechanics , financial economics , economics
The address discharge characteristics by the various scan‐low and common‐bias voltages are investigated based on measured address discharge time lags and V t close‐curve analysis. The scan‐low voltages are changed with the same voltage difference between the X and Y electrodes during an address period, meaning that the voltage difference between the scan‐low voltage applied to the Y electrode and the common‐bias voltage applied to the X electrode remains constant even though each voltage level changes. As the voltage difference between the scan and address electrodes is increased during an address period, the address discharge time lag is shortened but a high background luminance is induced. It is found that the improved address discharge characteristics is caused by the effect of the higher external applied voltage during an address period than the accumulated wall charges during a reset period and the high background luminance can be prevented by applying an address‐bias voltage during a rising‐ramp period.