Premium
P‐204L: Late‐News Poster : Analysis of Statistical Time Lags Based on Wall Charges Prior to Address Discharge Using Vt Close‐Curve Method for Full‐HD AC‐PDP
Author(s) -
Park Hyung Dal,
Kim Jae Young,
Tae HeungSik
Publication year - 2007
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2785364
Subject(s) - reset (finance) , plasma display , voltage , waveform , mechanics , electrical engineering , partial discharge , realization (probability) , time lag , materials science , lag , environmental science , chemistry , computer science , physics , electrode , mathematics , engineering , statistics , computer network , financial economics , economics
The high speed address is an important parameter to lower cost technology for the realization of full HD‐PDP. The wall charge supplied from the reset period is an important factor for affecting the fast and stable discharge characteristics during an address period. It is found that as the voltage level of the negative falling ramp in the reset waveform is lower, the accumulated wall charges during the ramp‐up period are more erased, thus reducing the amounts of wall charges prior to address discharge. The resultant changes in the address discharge characteristics were examined in the 42‐in. ac‐PDP with a high Xe (11 %) content. In particular, the measured Vt close‐curves and corresponding IR emission profiles show that less amounts of wall charges prior to an address discharge induce the decrease in the statistical time lag and total address discharge time lag in address period, thereby resulting in the stable and fast addressing. Therefore, it is advantageous to use the electric field from the applied voltage during an address discharge instead of utilizing the wall charges from the reset period for the stable and fast addressing.