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P‐41: 1.6Gbps Low‐Power Receiver for Display Interfaces Using a 3.3V and 0.35μm CMOS Process
Author(s) -
Kim JinHo,
Kwon OhKyong
Publication year - 2007
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2785301
Subject(s) - jitter , cmos , radio receiver design , signal (programming language) , electronic engineering , computer science , voltage , low voltage , swing , power (physics) , power consumption , low power electronics , bandwidth (computing) , electrical engineering , engineering , channel (broadcasting) , transmitter , telecommunications , physics , quantum mechanics , programming language , mechanical engineering
This paper proposes a low‐power receiver circuit that converts 1.6Gbps low‐voltage differential input signal with less than 100mV swing to CMOS level signal in a 0.35μm CMOS process. The proposed receiver enhances its bandwidth with low power consumption using the negative feedback circuit which is detecting input signal transient. HSPICE simulation results show that the power consumption of the proposed receiver at 1.6Gbps data recovery is less than 4mW, and the maximum jitter for 9‐bit PRBS input pattern is less than 10% of bit‐time. Compared to the previous LVDS receiver circuits, the proposed receiver can save more than 40% of power. In addition to the low‐power consumption, the proposed receiver has rail‐to‐rail input common‐mode voltage range.