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P‐9: Unified Model and Prediction Technique for On‐Current Degradation Caused by Drain‐Avalanche Hot Carriers in Low‐Temperature Poly‐Silicon Thin‐Film Transistors
Author(s) -
Kawamura Tetsufumi,
Matsumura Mieko,
Hatano Mutsuko,
Kaitoh Takuo,
Noda Takeshi,
Miyazawa Toshio,
Ohkura Makoto
Publication year - 2007
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2785264
Subject(s) - nmos logic , materials science , optoelectronics , transistor , degradation (telecommunications) , crystallinity , current (fluid) , silicon , thin film transistor , stress (linguistics) , voltage , engineering physics , electrical engineering , composite material , engineering , linguistics , philosophy , layer (electronics)
Abstract A unified model and a prediction technique for on‐current degradation in NMOS low‐temperature poly‐Silicon thin‐film transistors are presented. The resistance increase is expressed as a function of the stress‐drain current and stress‐drain voltage. This function is independent of the size, crystallinity, or initial characterization of the transistors. The turnaround time for circuit design can be shortened by using this technique.