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7.2: Realization of 6Mask LTPS CMOS Panel for AMLCD Application
Author(s) -
Park SooJeong,
Lee SeokWoo,
Kim YoungJoo,
Baek Myoung Kee,
Yoo Yong Su,
Lim Kyoung Moon,
Kim Chang Yeon,
Kim ChangDong,
Chung InJae
Publication year - 2007
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2785229
Subject(s) - cmos , thin film transistor , materials science , polycrystalline silicon , realization (probability) , transistor , doping , electrical engineering , optoelectronics , electronic engineering , engineering , nanotechnology , voltage , statistics , mathematics , layer (electronics)
6Mask CMOS process in low temperature polycrystalline silicon thin film transistors (poly‐Si TFTs) has been developed and verified by manufacturing a 6Mask CMOS panel. The 6Mask CMOS structure is suitable for the panel operation with line inversion, where a novel process is adopted to substitute for the storage doping of conventional structure without an additional mask step.