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Low‐power and small‐area holding latch with level‐shifting function using LTPS TFTs for mobile applications
Author(s) -
Choi JungHwan,
Kim YongJae,
Ahn SoonSung,
Kwon OhKyong
Publication year - 2007
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1889/1.2739797
Subject(s) - backplane , thin film transistor , logic level , liquid crystal display , power consumption , power (physics) , computer science , flat panel display , function (biology) , mobile device , materials science , electrical engineering , computer hardware , logic gate , optoelectronics , engineering , physics , layer (electronics) , algorithm , quantum mechanics , evolutionary biology , composite material , biology , operating system
— A holding latch having a level shifting function fabricated by using a low‐temperature polysilicon (LTPS) process with a 5‐μm design rule on a glass backplane for power and cost effectiveness has been proposed. The layout area and the power consumption of the proposed circuit are reduced by 10% and 52%, respectively, compared with those of a typical structure which combines a static D‐latch and a cross‐coupled level shifter for a 2.2‐in. qVGA TFT‐LCD panel.
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