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P‐52: A Panel Simulation Scheme of TFT‐LCDs for HDTV Applications
Author(s) -
Jung Chanyong,
Lee Jungbok,
Won Taeyoung,
Yoon SukIn,
Yoon SangHo
Publication year - 2006
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2433511
Subject(s) - thin film transistor , liquid crystal display , pixel , computer science , capacitor , transistor , capacitance , high definition television , flat panel display , parasitic capacitance , liquid crystal on silicon , electronic engineering , voltage , computer graphics (images) , electrical engineering , artificial intelligence , engineering , materials science , telecommunications , physics , electrode , layer (electronics) , quantum mechanics , operating system , composite material
In this paper, we propose a novel simulation scheme, which we call “block image simulation,” for the image analysis of a full thin film transistor liquid crystal display (TFT‐LCD) panel. The proposed approach makes it possible to estimate viewable image for varying conditions as well as electrical characteristics of a TFT‐LCD panel covering all the pixels. We also propose a compact circuit model for a TFT‐LCD pixel, which accounts for the parasitic capacitors present between the neighboring gate and data lines and voltage‐dependent liquid crystal (LC) pixel capacitance. In this work, we also report our successful simulation study on an exemplary 32 inch HDTV (1366 × 768) LCD panel in terms of crosstalk, shading, and gray scale error.