Premium
P‐217L: Late‐News Poster : An Analytical Lifetime Model for Digital a‐Si:H Circuits
Author(s) -
Li Zi,
Venugopal Sameer,
Shringarpure Rahul,
Allee David R.,
Clark Lawrence T.
Publication year - 2006
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2433475
Subject(s) - digital electronics , margin (machine learning) , electronic circuit , noise margin , noise (video) , electronic engineering , materials science , amorphous silicon , threshold voltage , computer science , voltage , electrical engineering , optoelectronics , silicon , engineering , transistor , artificial intelligence , machine learning , image (mathematics) , crystalline silicon
Digital circuits require positive static noise margin for correct operation. An analytical model of amorphous silicon digital circuit noise margin is described here. The model is verified with experimental measurements. The circuit aging effects that increase threshold voltage of a‐Si:H TFTs over time with electrical stress are used to determine the circuit lifetime under continuous operation.