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65.2: Spin‐On Polymers for TFT Gate Dielectric Application and Planarization of Stainless Steel
Author(s) -
Chen Jinghong,
Stifanos Mehari,
Fan Wenya,
Nedbal Jan,
Rose Jeff,
Krishnamoorthy Ahila,
Brouk Emma,
Smith Pete,
Daniels Brian
Publication year - 2006
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2433412
Subject(s) - materials science , chemical mechanical planarization , dielectric , thin film transistor , optoelectronics , gate dielectric , curing (chemistry) , wafer , hysteresis , polymer , voltage , composite material , electrical engineering , transistor , polishing , condensed matter physics , layer (electronics) , physics , engineering
We present spin‐on polymer films with significantly improved dielectric properties for TFT gate dielectric applications. Breakdown voltage//leakage current//CV hysteresis are 4.10 MV/cm at 1 μA/cm 2 //4.9 × 10 −8 A/cm 2 at 2.5 MV/cm//3.4 V and 4.73 MV/cm//2.6 × 10 −8 A/cm 2 //0.44V at curing temperatures of 250 °C and 425 °C, respectively. In addition, we present our recent results using spin‐on dielectrics to planarize and insulate stainless steel substrates for flexible displays and high resolution QVGA mobile displays.