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An LCOS IC layout verification method that uses a computational model for lithography manufacturing
Author(s) -
Koukharenko S. N.,
Volk S. V.,
Zayats A. M.,
Smirnov A. G.
Publication year - 2006
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1889/1.2235687
Subject(s) - computer science , lithography , computation , process (computing) , design for manufacturability , algorithm , mechanical engineering , optics , engineering , physics , operating system
— An advanced approach to LCOS IC layout verification is presented. It is based on incorporating the results of optical lithography computational models into the verification process. The first section describes an algorithm for the numerical modeling of optical lithography that uses a source integration method for computation of an aerial image. The second section dwells on an application of this algorithm for layout physical verification. A proposed physical verification method uses modeled contours of the manufactured elements to check whether a given layout will be manufacturable. The proposed verification method also considers deviations of manufactured contours from their modeled shapes due to variation of manufacturing parameters to further improve verification quality. At the same time, the method is conservative in terms of the use of a time‐consuming lithographical modeling.