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P‐168: LTPS PMOS Four‐Mask Process for AMLCDs
Author(s) -
Park Yong In,
Lee Dae Yoon,
Yoo Juhn S.,
Kang HoChul,
Lim Kyoung Moon,
Kim ChangDong,
Chung InJae
Publication year - 2005
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2036441
Subject(s) - pmos logic , materials science , thin film transistor , transistor , optoelectronics , active matrix , annealing (glass) , demultiplexer , electronic engineering , electrical engineering , engineering , nanotechnology , voltage , layer (electronics) , composite material , multiplexing , multiplexer
Simple p‐channel poly‐Si TFT (Thin Film Transistor) structure (PMOS 4mask structure) for AMLCD (active matrix liquid crystal display) was developed. Compared with a conventional PMOS 6mask process, two photo mask steps, passivation‐hole mask and pixel mask, has been eliminated to create 4mask process. Both ELA (Eximer Laser Annealing) and SLS (Sequential Lateral Solidification) method were used for the formation of a poly‐Si. By using PMOS 4mask process, 10.4‐inch XGA (1024×768) AMLCD panel with integration of the gate‐driver and demultiplexer was successfully realized.