24.4: A 510‐Kb SOG‐DRAM for Frame‐Memory‐Integrated Displays | Zendy

Haga Hiroshi | Zendy; aka Yoshihiro | Zendy; Kitagishi Youichi | Zendy; Kamon Youichiro | Zendy; Matsuzaki Tadahiro | Zendy; Sato Yoshinobu | Zendy; Asada Hideki | Zendy; Otose Tomohiko | Zendy; Sasaki Daigo | Zendy

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24.4: A 510‐Kb SOG‐DRAM for Frame‐Memory‐Integrated Displays

Author(s) -

Haga Hiroshi,

aka Yoshihiro,

Kitagishi Youichi,

Kamon Youichiro,

Matsuzaki Tadahiro,

Sato Yoshinobu,

Asada Hideki,

Otose Tomohiko,

Sasaki Daigo

Publication year - 2005

Publication title -

sid symposium digest of technical papers

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.351

H-Index - 44

eISSN - 2168-0159

pISSN - 0097-966X

DOI - 10.1889/1.2036194

Subject(s) - dram , computer science , frame (networking) , reading (process) , codec , computer hardware , chip , memory controller , embedded system , semiconductor memory , telecommunications , political science , law

A system‐on‐glass (SOG) DRAM intended for integrated frame‐memories of 262k‐color QCIF+ displays has been developed. An integrated codec circuit reduces the number of memory cells and layout area by a factor of 2/3. By combining the SOG‐DRAM, which has a data retention time of over 16.6 ms, with an embedded controller that enables simultaneous access for writing and reading, a frame‐memory has been created. The operation was verified by chip measurement and demonstration.

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