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21.1: Common‐Decoder Architecture for Compact and Power‐Saving Poly‐Si Data‐Driver Circuits
Author(s) -
Kageyama Hiroshi,
Miyamoto Mitsuhide,
Akimoto Hajime,
Nishitani Shigeyuki,
Sato Toshihoro,
Miyazawa Toshio
Publication year - 2005
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.2036177
Subject(s) - amoled , electronic circuit , computer science , driver circuit , computer hardware , power consumption , signal integrity , electronic engineering , power (physics) , electrical engineering , engineering , printed circuit board , materials science , active matrix , voltage , physics , layer (electronics) , quantum mechanics , composite material , thin film transistor
We have proposed the common‐decoder architecture for a data‐driver circuit fabricated by using a poly‐Si process: the architecture achieves a compact circuit and low power consumption. In application to a 6‐bit data driver, this architecture replaces the 6‐bit vertical bus lines that occupy a large area of the conventional DAC with two vertical signal lines. It also suppresses the power consumption of the data bus by reducing the number of bits inverted in word‐to‐word transitions from six to two. We fabricated an AMOLED panel with an integrated 6‐bit data‐driver circuit having 384 outputs, using a conventional 4‐micron design rule. The driver circuit had a height of 2.6 mm and a pitch between output lines of 84 microns. We confirmed that the driver's maximum power consumption was only 5 mW and that the AMOLED panel showed smooth 64‐level gray‐scale characteristics. Furthermore, we fabricated an AMLCD panel including driver circuits of the same type as integrated elements. Six‐bit full‐color images were successfully displayed on both panels.