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Analysis of dynamic characteristics in a‐Si TFT structures
Author(s) -
Kitazawa Tomoko,
Shibusawa Makoto,
Higuchi Toyoki
Publication year - 1993
Publication title -
journal of the society for information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.578
H-Index - 52
eISSN - 1938-3657
pISSN - 1071-0922
DOI - 10.1889/1.1984859
Subject(s) - thin film transistor , materials science , threshold voltage , optoelectronics , voltage , spice , pulse (music) , transistor , electrical engineering , nanotechnology , layer (electronics) , engineering
— The dynamic characteristics of a‐Si TFTs in terms of level shift in pixel voltage have been investigated in various TFT structures, such as back‐channel‐etched (BCE) TFTs, tri‐layered (TL) TFTs, and self‐aligned (SA) TFTs. The dependence of the level‐shift voltage on drain voltage and on gate‐pulse delay was measured. The results were compared to that of SPICE simulation. When the gate‐pulse delay is zero, the drain‐voltage dependence of the level shift for the BCE TFT is larger than that of the level shifts for the TL TFT and the SA TFT. On the other hand, when the gate‐pulse delay increases, the level shift drastically decreases, and the magnitude of the decrease is independent of the three TFT structures.