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27.3: Improvement of Electrical Stability of Poly‐Si TFTs Using Vertical a‐Si Offset
Author(s) -
Park K.C.,
Yoo J.S.,
Kim C.H.,
Han M.K.,
Choi K.Y.
Publication year - 1999
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1834040
Subject(s) - thin film transistor , materials science , polycrystalline silicon , optoelectronics , recrystallization (geology) , amorphous solid , oxide thin film transistor , excimer laser , silicon , photolithography , amorphous silicon , transistor , thin film , laser , composite material , nanotechnology , crystalline silicon , optics , electrical engineering , crystallography , voltage , paleontology , chemistry , physics , layer (electronics) , biology , engineering
Polycrystalline silicon (poly‐Si) thin film transistors (TFT's) employing vertical amorphous silicon (a‐Si) offsets have been fabricated without additional photolithography processes. The a‐Si offset has been formed utilizing the poly‐Si grain growth blocking effect by thin native oxide film during the excimer laser recrystallization of a‐Si. The ON current degradation of the new device after 4 hour's electrical stress, was reduced by at least 5 times compared with conventional poly‐Si TFT's.