Premium
Reduction of Data Pulse Voltage to 20V by Using Address‐while‐Display Scheme for AC‐PDPs
Author(s) -
Ishii M.,
Igarashi K.,
Mikoshiba S.,
Asai H.,
Sago S.
Publication year - 1999
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1833985
Subject(s) - reduction (mathematics) , voltage , materials science , duty cycle , optoelectronics , pulse (music) , electrode , scheme (mathematics) , key (lock) , data reduction , electrical engineering , computer science , chemistry , engineering , mathematics , mathematical analysis , geometry , computer security , data mining
Data pulse voltage for the 3‐electrode, surface‐discharge AC‐PDP is reduced to less than 20V by using Address‐while‐Display scheme which is capable of attaining 96% light‐emission duty. Metastable atoms created in each sub‐field play the key role to the voltage reduction.