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High‐performance top‐gate a‐Si:H TFTs for AMLCDs
Author(s) -
Chiang ChunSung,
Martin Sandrine,
Nahm JeongYeop,
Kanicki Jerzy,
Ugai Yasuhiro,
Yukawa Teizo,
Takeuchi Shu
Publication year - 1998
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1833773
Subject(s) - thin film transistor , materials science , plasma enhanced chemical vapor deposition , optoelectronics , amorphous silicon , amorphous solid , transistor , silicon , electrical engineering , nanotechnology , layer (electronics) , voltage , crystalline silicon , crystallography , chemistry , engineering
Abstract High‐performance top‐gate hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) structures have been fabricated over a large area from plasma‐enhanced chemical vapor deposition (PECVD) materials. The electrical performances of the top‐gate a‐Si:H TFT (μ FE ≅0.75cm 2 /Vsec, V T ≅3.5V, S ≅0.55V/dec) are comparable to the electrical performances observed for an inverted‐staggered bottom‐gate a‐Si:H TFT. We have shown that the TFT field‐effect mobility first increases with the a‐Si:H thickness, and then decreases for thicker a‐Si:H films. This change of the electrical performances can be associated either with the variation of a‐Si:H microstructure with film thickness during the PECVD processes or a large density of TFT back interface states; it also involves the source/drain parasitic access resistances, especially for thick a‐Si:H layers.