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6.5L: Late‐News Paper : Design for Super‐Resolution Image Processing Using a Parallel Image Processor Chip Set
Author(s) -
Greenberg Robert,
Decker Les
Publication year - 2000
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1833002
Subject(s) - scalability , computer science , chip , set (abstract data type) , resolution (logic) , image processing , bandwidth (computing) , image (mathematics) , computer hardware , display resolution , computer vision , artificial intelligence , telecommunications , display device , operating system , database , programming language
This design provides a solution for super resolution display that overcomes current bandwidth limitations. The display is essentially split into two halves, with each half driven by a PW364 ImageProcessor. The design is versatile in handling multiple input signals and scalable for even higher resolution displays. It uses mass‐produced components that reduce costs and enable faster time to market.