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46.1: Invited Paper: Interface — The Key to High‐Performance Poly‐Si TFT Fabrication
Author(s) -
Higashi Seiichiro,
Abe Daisuke,
Miyashita Kazuyuki,
Kawamura Takahiro,
Inoue Satoshi,
Shimoda Tatsuya
Publication year - 2003
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1832525
Subject(s) - thin film transistor , fabrication , materials science , polycrystalline silicon , optoelectronics , transistor , interface (matter) , threshold voltage , swing , grain boundary , subthreshold swing , subthreshold conduction , key (lock) , silicon , voltage , electrical engineering , nanotechnology , computer science , layer (electronics) , engineering , composite material , microstructure , alternative medicine , computer security , capillary number , capillary action , pathology , medicine , mechanical engineering
Low temperature process technologies for high‐performance polycrystalline Si (poly‐Si) thin‐film transistor (TFT) fabrication are discussed based on a key word — “interface”. Reduction of localized defects at two types of interfaces, namely grain boundary in poly‐Si film and gate SiO 2 /Si interface, successfully achieves high‐performance poly‐Si TFTs with average n‐channel mobility of 315 cm 2 V −2 s −2 , threshold voltage (V th ) of 0.86 V and subthreshold swing (S) of 143 mV/decade with small variations (1σ) of 30 cm 2 V −2 s −2 , 0.05 V and 6 mV/decade, respectively. This result indicates that control of “interface” is the key to the next generation high‐performance poly‐Si TFT fabrication.