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P‐36: Block‐dim Free Driving Options for TFT Panels with PCB‐less or COG Gate Driver
Author(s) -
Buchschacher Pascal,
Daum Martin
Publication year - 2003
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1832279
Subject(s) - thin film transistor , block (permutation group theory) , printed circuit board , capacitor , electrical engineering , line (geometry) , track (disk drive) , engineering , automotive engineering , computer science , computer hardware , materials science , voltage , mechanical engineering , composite material , mathematics , layer (electronics) , geometry
Abstract New low cost assembly techniques for TFT gate drivers GDs use on‐glass track to replace traditional printed circuit board PCB wiring. Row return currents then induce excessive voltage disturbances because the sheet resistance of on‐glass track is roughly 100 times higher than before. TFT panels with storage capacitor Cst on the previous gate line are badly affected when driven by conventional 2‐level GDs. Horizontal gray areas of different intensity block‐dim appear when an asymmetrical pattern is displayed. This paper reviews known techniques to suppress block‐dim and proposes a new solution for standard TFT panels.