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P‐9: Ion‐Doping Process Using a Hard Gate Mask in Low‐Temperature Poly‐Si TFT Fabrication
Author(s) -
Lee Ryan,
Tsai ChengHsun,
Chiang DienShen,
Chang ShihChang,
Tsai YawMing
Publication year - 2003
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1832246
Subject(s) - thin film transistor , nmos logic , materials science , pmos logic , polycrystalline silicon , optoelectronics , doping , etching (microfabrication) , fabrication , silicon on insulator , silicon , electrical engineering , transistor , nanotechnology , voltage , engineering , medicine , alternative medicine , layer (electronics) , pathology
A new low‐temperature polycrystalline‐silicon LTPS process was developed. The doping mask for p‐type TFT was compared with PR mask and gate hard mask. The process and design challenge in gate hard mask was compared with the photo resist residues problem encountered in PR mask process. In the gate hard mask technology, the gates of p‐type and n‐type TFTs are etched in different steps for p‐type TFT S/D doping and n‐type TFT LDD doping. The results indicate the gate insulator loss and the CD loss due to these different etching steps can be controlled in the same magnitude, and the TFT electrical characteristics of NMOS and PMOS are good enough for pixel and driver applications.