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49.2: Reduction of Power Consumption in Address Driver ICs for PDP by Power Distributing Method
Author(s) -
Sano Y.,
Takagi A.,
Kawada T.,
Inoue H.,
Kariya K.,
Sugimoto Y.
Publication year - 2001
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1831782
Subject(s) - power consumption , reduction (mathematics) , power (physics) , computer science , energy consumption , resolution (logic) , cost reduction , embedded system , electrical engineering , engineering , business , mathematics , artificial intelligence , physics , geometry , marketing , quantum mechanics
We herewith propose Power distributing method, which enables the reduction of power consumption in address driver ICs with cost‐effective way even for the large‐size and high‐resolution panel. By this method the cost of address driver circuit can be reduced by around 30% compared with the energy recovery method.