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P‐4: Investigation on the Correlation between Layout Parameters and ESD Robustness of LTPS TFT Devices
Author(s) -
Chu FangTsun,
Tseng HuaiYuan,
Chen ChenMing,
Chen ChengChung,
Yeh YungHui,
Hou ChunLin,
Chang ChihYih
Publication year - 2004
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1830957
Subject(s) - electrostatic discharge , robustness (evolution) , thin film transistor , electronic engineering , electronic circuit , materials science , transmission line , electrical engineering , computer science , engineering , voltage , nanotechnology , biochemistry , chemistry , layer (electronics) , gene
The electrostatic discharge (ESD) characteristics and robustness of LTPS TFT devices with different layout parameters were investigated in this paper. Several key layout parameters and device structures, such as device channel length/width, drain contact to gate spacing, contact layout geometry, gate‐overlap structure and LDD length…etc, were designed to characterize the device ESD performance by using both electrostatic discharge simulator (ETS‐910) and transmission line pulsing generator (TLPG) system. The ESD induced failure phenomena were also discussed. These layout dependent results on ESD robustness of LTPS TFTs would help designers implement the ESD protection devices or circuits on the panel of glass substrate.