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P‐2: A Novel Self‐Aligned SiGe Elevated S/D polycrystalline‐Silicon Thin‐Film Transistor
Author(s) -
Peng DuZen,
Shih PoSheng,
Zan HsiaoWen,
Chang ChunYen,
Chang TingChang,
Lin ChiungWei
Publication year - 2002
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1889/1.1830231
Subject(s) - thin film transistor , materials science , polycrystalline silicon , transistor , optoelectronics , silicon , chemical vapor deposition , thin film , nanotechnology , voltage , electrical engineering , layer (electronics) , engineering
A novel self‐aligned SiGe elevated source and drain (S/D) poly‐Si thin film transistor (poly‐Si TFT) was fabricated. The elevated source and drain regions were selectively grown by ultra‐high vacuum chemical vapor deposition (UHVCVD) at 550°C. The resultant transistor has a thin channel region and a self‐aligned thick S/D region, which leads to better performance. With this structure, the turn‐on current in the I‐V characteristics increases dramatically and the drain breakdown voltage is increased as well, compared with conventional thin‐channel poly‐Si TFTs.