Open AccessMasking of Internal Nodes Faults Based on Applying of Incompletely Specified Boolean Functions
Author(s) -
Angela Yu. Matrosova,
V. Provkin,
V. Andreeva
Publication year - 2020
Publication title -
izvestiâ saratovskogo universiteta. novaâ seriâ. seriâ matematika. mehanika. informatika
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.255
H-Index - 4
eISSN - 2541-9005
pISSN - 1816-9791
DOI - 10.18500/1816-9791-2020-20-4-517-526
Subject(s) - boolean function , combinational logic , overhead (engineering) , computer science , electronic circuit , masking (illustration) , boolean circuit , algorithm , node (physics) , frame (networking) , function (biology) , fault (geology) , logic gate , engineering , electrical engineering , art , structural engineering , evolutionary biology , seismology , geology , visual arts , biology , operating system , telecommunications
Combinational circuits (combinational parts of sequential circuits) are considered. Masking of internal nodes faults with applying sub-circuit, inputs of which are connected to the circuit inputs and outputs — to the circuit proper internal nodes, is suggested. The algorithm of deriving incompletely specified Boolean function for an internal node of the circuit based on using operations on ROBDDs is described. Masking circuit (patch circuit) design for the given internal fault nodes is reduced to covering of the system of incompletely specified Boolean functions corresponding to the fault nodes by the proper SoP system. Then the obtained system of completely specified Boolean functions is applied to derive masking circuit by using ABC system (A System for Sequential Synthesis and Verification). Experiments on bench marks show essential cutting of overhead in the frame of the suggested approach.